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1 ?2017 integrated device technology, inc. revision e, january 10, 2017 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 sel0 sel1 nc nc clk nclk nc mr gnd q nq v ddo gnd qfb nqfb v ddo nc v dd nfb_in fb_in sel2 gnd nc nc v dd pll_sel v dda sel3 nc nc nc nc general description the 8745bi-21 is a highly versatile 1:1 lvds clock generator. the 8745bi-21 has a fully integrated pll and can be configured as a zero delay buffer, multiplier or di vider, and has an output frequency range of 31.25mhz to 700mhz. the reference divider, feedback divider and output divider ar e each programmable, thereby allowing for the following output-to-i nput frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1: 8. the external feedback allows the device to achieve ?zero delay? between the input clock and the output clock. the pll_sel pin can be used to by pass the pll for system test and debug purposes. in bypass mode, the reference clock is routed around the pll and into the internal output dividers. features ? one differential lvds output designed to meet or exceed the requirements of ansi tia/eia-644 one differential feedback output pair ? differential clk, nclk input pair ? clkx, nclkx pair can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl, sstl ? output frequency range: 31.25mhz to 700mhz ? input frequency range: 31.25mhz to 700mhz ? vco range: 250mhz to 700mhz ? external feedback for ?zero delay? clock regeneration with configurable frequencies ? programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 ? cycle-to-cycle jitter: 30ps (maximum) ? output skew: 40ps (maximum) ? static phase offset: 25ps 125ps ? full 3.3v supply voltage ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package ? for functional replacement part use 8t49n285 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 qfb nqfb v ddo sel2 fb_in nfb_in mr nclk clk gnd sel1 sel0 v dd pll_sel v dda sel3 gnd q nq v ddo 8745bi-21 20-lead soic 7.5mm x 12.8mm x 2.3mm package body m package top view block diagram pll_sel clk clk fb_in fb_in sel0 sel1 sel2 sel3 mr q q qfb qfb pll 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 0 1 1, 2, 4, 8, 16, 32 , 64 pullup pullup pulldown pullup pulldown pullup pulldown pulldown pulldown pulldown pulldown pulldown pin assignments pr o pose d ics8745bi-21 32 lead vfqfn 5mm x 5mm x 0.925mm package body k package top view 8745bi-21 datasheet 1:1 differential-to-lvds zero delay clock generator
2 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1 clk input pulldown non-inverting differential clock input. 2 nclk input pullup inverting differential clock input. 3 mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the true output q to go low and the inverted output nq to go high. when logic low, the internal dividers and the outputs are enabled. lvcmos / lvttl interface levels. 4nfbin input pullup inverting differential feedback input to phase detector for regenerating clocks with ?zero delay.? 5 fbin input pulldown non-inverted differential feedback input to phase detector for regenerating clocks with ?zero delay.? 6, 15, 19, 20 sel2, sel3, sel0 sel1 input pulldown determines output divider values in table 3. lvcmos / lvttl interface levels. 7, 11 v ddo power output supply pins. 8, 9 nqfb/qfb output differential feedback output pair. lvds interface levels. 10, 14 gnd power power supply ground. 12, 13 nq/q output differential output pair. lvds interface levels. 16 v dda power analog supply pin. 17 pll_sel input pullup pll select. selects between the pll and reference clock as the input to the dividers. when low, selects reference clock. lvcmos/lvttl interface levels. 18 v dd power core supply pin. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
3 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet function tables table 3a. control input function table *note: vco frequency range for all config urations above is 250mhz to 700mhz. inputs outputs pll_sel = 1 pll enable mode sel3 sel2 sel1 sel0 reference frequency range (mhz)* q, nq 0000 250 - 700 1 0001 125 - 350 1 0010 62.5 - 175 1 0011 31.25 - 87.5 1 0100 250 - 700 2 0101 125 - 350 2 0110 62.5 - 175 2 0111 250 - 700 4 1000 125 - 350 4 1001 250 - 700 8 1010 125 - 350 x2 1011 62.5 - 175 x2 1100 31.25 - 87.5 x2 1101 62.5 - 175 x4 1110 31.25 - 87.5 x4 1111 31.25 - 87.5 x8
4 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet table 3b. pll bypass function table inputs outputs pll_sel = 0 pll bypass mode sel3 sel2 sel1 sel0 q, nq 0000 4 0001 4 0010 4 0011 8 0100 8 0101 8 0110 16 0111 16 1000 32 1001 64 1010 2 1011 2 1100 4 1101 1 1110 2 1111 1
5 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operat ion of product at these condit ions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. lvds power supply dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current surge current 10ma 15ma package thermal impedance, ? ja 20 lead soic package 32 lead vfqfn package 46.2 ? c/w (0 lfpm) 37 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current 128 ma i dda analog supply current 18 ma i ddo output supply current 62 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current sel[0:3], mr v dd = v in = 3.465v 150 a pll_sel v dd = v in = 3.465v 5 a i il input low current sel[0:3], mr v dd = 3.465v, v in = 0v -5 a pll_sel v dd = 3.465v, v in = 0v -150 a proposed
6 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet table 4c. differential dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . table 4d. lvds dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c table 5. input frequency characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units i ih input high current clk, fb_in v dd = v in = 3.465v 150 a nclk, nfb_in v dd = v in = 3.465v 5 a i il input low current clk, fb_in v dd = 3.465v, v in = 0v -5 a nclk, nfb_in v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 gnd + 0.5 v dd ? 0.85 v symbol parameter test conditio ns minimum typi cal maximum units v od differential output voltage 320 440 550 mv ? v od v od magnitude change 0 50 mv v os offset voltage 1.05 1.2 1.35 v ? v os v os magnitude change 25 mv symbol parameter test conditions minimum typical maximum units f in input frequency clk, nclk pll_sel = 1 31.25 700 a pll_sel = 0 700 v
7 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet ac electrical characteristics table 6. ac characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed ov er the specified ambient operating temper ature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. th e device will meet specifications after thermal equilibrium has been reached under these conditions. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as the time difference between the input reference clock and the averaged feedback input signal across all cond itions, when the pll is locked and the input reference frequency is stable. note 3: defined as skew between outputs at the same supply volta ge and with equal load conditions . measured at the output diffe rential cross points. note 4: phase jitter is dependent on the input source used. note 5: this parameter is defined in accordance with jedec standard 65. note 6: characterized at vco frequency of 622mhz. note 7: measured from the 20% to 80% points. guar anteed by characterization. not production tested. symbol parameter test conditio ns minimum typical maximum units f max output frequency 700 mhz t pd propagation delay; note 1 pll_sel = 0v, f ? 700mhz 2.9 3.4 4.0 ns t sk(?) static phase offset; note 2, 5 pll_sel = 3.3v -100 25 150 ps t sk(o) output skew; note 3, 5 40 ps t jit(cc) cycle-to-cycle jitter; note 5, 6 30 ps t jit( ? ) phase jitter; note 4, 5, 6 52 ps t l pll lock time 1ms t r / t f output rise/fall time; note 7 20% to 80% 200 700 ps odc output duty cycle 45 50 55 %
8 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet parameter measureme nt information 3.3v lvds output load ac test circuit phase jitter and static phase offset cycle-to-cycle jitter differential input level output skew output rise/fall time scope q nq 3.3v5% power supply +? float gnd v dda, v ddo v dd, nclk clk nfb_in fb_in ? ? t (?) v oh v ol v o h v o l t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles q nq nclk clk v dd gnd v cmr cross points v pp qx nqx qy nqy 20% 80% 80% 20% t r t f v od q nq
9 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet parameter measure ment information, continued output duty cycle offset voltage setup propagation delay differential output voltage setup q nq nq q nclk clk t pd
10 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet applications information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is required. the 8745bi-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd, v dda and v ddo should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 ? resistor along with a 10 ? f bypass capacitor be connected to the v dda pin. figure 1. power supply filtering wiring the differential input to accept single-ended levels figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specific ations are characterized and guaranteed by using a differential signal. figure 2. recommended schematic for wiring a di fferential input to accept single-ended levels v dd v dda 3.3v 10 10 f .01f .01f
11 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both diff erential signals must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces sugge sted here are examples only. please consult with the vendor of t he driver component to confirm the driver termination requirements. for example, in figure 3a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from anot her vendor, use their termination recommendation. 3a. clk/nclk input driven by an idt open emitter lvhstl driver figure 3c. clk/nclk input driven by a 3.3v lvpecl driver figure 3e. clk/nclk input driven by a 3.3v hcsl driver figure 3b. clk/nclk input driven by a 3.3v lvpecl driver figure 3d. clk/nclk input driven by a 3.3v lvds driver figure 3f. clk/nclk input driven by a 2.5v sstl driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differenti al input hcsl *r3 *r4 clk nclk 3.3v 3.3v differential input clk nclk differenti al input sstl 2.5v zo = 60 zo = 60 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
12 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but ca n be added for additional protection. a 1k ? resistor can be used. clk/nclk input for applications not requiring the us e of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. outputs: lvds output all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left float ing, we recommend that there is no trace attached. lvds driver termination a general lvds interface is shown in figure 4. standard termination for lvds type output st ructure requires both a 100 ? parallel resistor at the receiver and a 100 ? differential transmission line environment. in order to avoid any transmission line reflection issues, the 100 ? resistor must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source an d voltage source. the standard termination schematic as shown in figure 4 can be used with either type of output structure. if usi ng a non-standard termination, it is recommended to contact idt and confirm if the output is a current source or a voltage source type st ructure. in addition, since these outputs are lvds compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. figure 4. typical lvds driver termination 100 ? + 100 differential transmission line lvds driver lvds receiver
13 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) wit hin the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 5. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the out er edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from t he package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirement s. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further informati on, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 5. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
14 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet schematic example the schematic of the 8745bi-21 layout example is shown in figure 6a. the 8745bi-21 recommended pcb board layout for this example is shown in figure 6b. this layout example is used as a general guideline. the layout in the actual system wi ll depend on the selected component types, the density of the components, the density of the traces, and the stack up of the p.c. board. figure 6a. 8745bi-21 lvds zero delay buffer schematic example sel2 pll_sel rd6 sp rd4 sp r4 100 vdd ru3 1k sp = space (i.e. not intstalled) sel0 sel3 ru4 1k sel[3:0] = 0101, divide by 2 r8 50 rd7 1k (77.76 mhz) vddo vdd c1 0.1uf bypass capacitors located near the power pins ru5 sp c16 10u sel3 vddo (u1-7) zo = 50 ohm vdda 3.3v pecl driver sel1 r9 50 vdd=3.3v vddo r10 50 sel0 zo = 50 ohm rd5 1k c11 0.01u (u1-11) c4 0.1uf sel2 (155.52 mhz) lvds_input + - zo = 100 ohm differential r2 100 sel1 ru7 sp c2 0.1uf r7 10 pll_sel u1 ics8745b-21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 clk nclk mr nfb_in fb_in sel2 vddo nqfb qfb gnd vddo nq q gnd sel3 vdda sel1 sel0 vddi pll_sel rd3 sp vdd vddo=3.3v ru6 1k 3.3v
15 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet the following component footprints are used in this layout example. all the resistors and capacitors are size 0603. power and grounding place the decoupling capacitors as close as possible to the power pins. if space allows, placement of the decoupling capacitor on the component side is preferred. th is can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. maximize the power and ground pad sizes and number of vias capacitors. this can reduce the inductance between the power and ground planes and the component power and ground pins. the rc filter consisting of r7, c11, and c16 should be placed as close to the v dda pin as possible. clock traces and termination poor signal integrity can degrade the system performance or cause system failure. in synchronous high-speed digital systems, the clock signal is less tolerant to poor signa l integrity than other signals. any ringing on the rising or falling edge or excessive ring back can cause system failure. the shape of the trace and the trace delay might be restricted by the available space on the board and the component location. while routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. ? the differential 50 ? output traces should have the same length. ? avoid sharp angles on the clock trace. sharp angle turns cause the characteristic impedance to change on the transmission lines. ? keep the clock traces on the same layer. whenever possible, avoid placing vias on the clock traces. placement of vias on the tr aces can affect the trace characteristic impedance and hence degrade signal integrity. ? to prevent cross talk, avoid routing other signal traces in parallel with the clock traces. if running parallel traces is unavoidable, allow a separatio n of at least three trace widths between the differential clock trace and the other signal trace. ? make sure no other signal traces are routed between the clock trace pair. ? the matching termination resistors should be located as close to the receiver input pins as possible. figure 6b. pcb board layout for 8745bi-21 100 ohm differential traces vdda vdd c2 u1 r7 c16 vddo gnd c4 c1 ics8745b-21 via c11
16 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet power considerations this section provides information on power dissipa tion and junction temperature for the 8745bi-21. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8745bi-21 is the sum of the co re power plus the analog power plus the power dissipated in t he load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.465v * (128ma + 18ma) = 506mw ? power (outputs) max = v ddo_max * i ddo_max = 3.465v * 62ma = 215mw total power_ max = 506mw + 215mw = 721mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad dire ctly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (e xample calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the a ppropriate value is 46.2c/w per table 7a below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.721w * 46.2c/w = 118.3c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary dep ending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7a. thermal resistance ? ja for 20 lead soic, forced convection table 7b. thermal resistance ? ja for 32 lead vfqfn, forced convection ? ja vs. air flow linear feet per minute 0 200 500 single-layer pcb, jedec standard te st boards 83.2c/w 65.7c/w 57.5c/w multi-layer pcb, jedec standard test boards 46.2c/w 39.7c/w 36.8c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 37.0c/w 32.4c/w 29.0c/w p ropos e d
17 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet reliability information table 8a. ? ja vs. air flow table for a 20 lead soic table 8b. ? ja vs. air flow table for a 32 lead vfqfn transistor count the transistor count for 8745bi-21 is: 2772 package outline and package dimensions package outline - m suffix for 20 lead soic table 9a. package dimensions for 20 lead soic reference document: jedec publication 95, ms-013, ms-119 ? ja vs. air flow linear feet per minute 0 200 500 single-layer pcb, jedec standard te st boards 83.2c/w 65.7c/w 57.5c/w multi-layer pcb, jedec standard test boards 46.2c/w 39.7c/w 36.8c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 37.0c/w 32.4c/w 29c/w 300 millimeters all dimensions in millimeters symbol minimum maximum n 20 a 2.65 a1 0.10 a2 2.05 2.55 b 0.33 0.51 c 0.18 0.32 d 12.60 13.00 e 7.40 7.60 e 1.27 basic h 10.00 10.65 h 0.25 0.75 l 0.40 1.27 ? 0 7 proposed
18 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet package outline and package dimensions package outline - k suffix for 32 lead vfqfn t able 9b. package dimensions reference document: jedec publication 95, mo-220 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 9b. to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or anvil singulation n-1 n chamfer 1 2 n-1 1 2 n radius 4 4 bottom view w/type c id bottom view w/type a id there are 2 methods of indicating pin 1 corner at the back of the vfqfn package: 1. type a: chamfer on the paddle (near pin 1) 2. type c: mouse bite on the paddle (near pin 1) jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum nominal maximum n 32 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.25 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.40 0.50 p rop os e d
19 ?2017 integrated device technology, inc. revision e, january 10, 2017 8745bi-21 datasheet ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configur ation and are rohs compliant. revision history sheet part/order number marking package shipping packaging temperature 8745bmi-21 ICS8745BMI-21 20 lead soic tube -40 ? c to 85 ? c 8745bmi-21t ICS8745BMI-21 20 lead soic tape & reel -40 ? c to 85 ? c 8745bmi-21lf ICS8745BMI-21lf ?lead-free? 20 lead soic tube -40 ? c to 85 ? c 8745bmi-21lft ics8745bmi-2 1lf ?lead-free? 20 lead soic tape & reel -40 ? c to 85 ? c 8745bki-21lf ics745bi21l ?lead-free? 32 lead vfqfn tray -40 ? c to 85 ? c 8745bki-21lft ics745bi21l ?lead-free? 32 lead vfqfn tape & reel -40 ? c to 85 ? c rev table page description of change date b t4d 5 lvds dc characteristics table - modified vos 0.90v min. to 1.05v min, 1.15v typical to 1.2v typical, and 1.4v max. to 1.35v max. 3/17/04 c t6 7 12 15 ac characteristics table - changed t pd max limit from 3.9ns to 4.0ns. added recommendations for un used input & output pins. added power considerations section. updated format throughout the datasheet. 4/17/07 c t3a t 3b t4c t6 t10 1 3 4 6 7 10 11 17 pin assignment - corrected lineup of pin names. control input function table - deleted ?z? from 1st row of sel3 column. pll bypass function table - deleted ?z? from 1st row of sel3 column differential dc characterist ics table - updated notes. ac characteristics table - added thermal note. power supply filtering tech nique - updated paragraph. updated differential clock input interface. ordering information table - added ?lf? marking. deleted ?ics? prefix in part/order number column. updated header/footer of datasheet. 1/25/10 d t7b t8b t9b t10 1 5 10 12 13 16 17 18 19 added 32 lead vfqfn proposed pin assignment. absolute maximum ratings - added 32 lead vfqn package thermal impedance. updated wiring the differential input to accept single-ended levels. updated lvds output termination. added vfqfn epad thermal release section. added proposed 32 lead vfqfn thermal resistance table. added proposed 32 lead vfqfn theta ja table. added proposed 32 lead vfqfn package outline and dimensions. ordering information table added proposed 32 lead vfqfn ordering information. 7/28/10 d1 product discontinuation notice - last time buy expires november 2, 2016. pdn# cq-15-05. 11/6/15 e per pdn# cq-15-05 obs olete datasheet. 1/10/17 p r opos e d
disclaimer integrated device technology, in c. (idt) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of idt's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not conv ey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . copyright ?2017 integrated device tec hnology, inc. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com

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